1. Field of the Invention
The present invention relates to semiconductor device and a fabricating method of same, and more particularly, to a semiconductor device and a fabricating method of same having a reduced step difference between a DRAM cell region and a logic device region.
2. Discussion of the Related Art
As integration and density of semiconductor devices increases and memory cell area decreases, increasing the density of capacitors having a high charge storage capacity becomes increasingly important. In order to increase the capacitance of each capacitor, a surface area of a dielectric is increased by forming a capacitor having either a stacked structure or a threedimensional trench.
A device having both a DRAM cell and a logic device integrated on a single chip is formed by combining a known process of fabrication of the DRAM cell with a known process of fabrication of the logic device.
FIG. 1 shows a cross-sectional view of a conventional semiconductor device. A field oxide film 13 defining an active area is formed on a p-type semiconductor substrate 11. A transistor having a gate 19 and source/drain junctions 15, 17 doped heavily with N-type impurities is formed on an active area on the substrate 11. The gate 19 is surrounded by an insulating layer 21 and is isolated from the substrate 11.
A bit line 23 is formed in contact with the drain junction 17. The insulating layer 21, an insulating interlayer 24 on the bit line 23, a planarized layer 25, and an etch-stop layer 27 are formed sequentially, and then a contact hole 29 exposing the source junction 15 is formed by etching the etch-stop layer 27, the planarized layer 25 and the insulating interlayer 24. A storage electrode 31 of a capacitor is formed with doped polycrystalline silicon, and a lower portion of the storage electrode 31 is in contact with the source junction 15. The storage electrode 31 fills the contact hole 29, and an upper portion of the storage electrode 31 having a crown shape is formed on the etch-stop layer 27.
A dielectric film 37 including oxide or nitride/oxide is formed on a surface the storage electrode 31, and then a plate electrode 39 is formed on the dielectric film 37.
FIGS. 2A to 2D show cross-sectional views of a conventional process for fabricating the semiconductor device. Referring to FIG. 2A, a transistor is formed on the active area defined by the field oxide film 13 on the P-type semiconductor substrate 11. The transistor includes the gate 19 surrounded by an insulating layer 21 and isolated from the substrate 1, and source/drain junctions 15, 17. The bit line 23 is formed in contact with the drain junction 17. The insulating interlayer 24 including oxide is formed over a surface of the entire structure, and the planarized layer 25 is formed on the interlayer 24 by depositing a material having good flow characteristics, such as, for example, PSG (Phospho Silicate Glass), BSG (Boro Silicate Glass) and BPSG (Boro Phospho Silicate Glass).
An etch-stop layer 27 is formed by depositing a material having a different etch selectivity from the planarized layer 25 on the planarized layer 25. The contact hole 29 is formed using photolithography to expose the source junction 15 by removing portions of the etch-stop layer 27, the planarized layer 25 and the insulating interlayer 24.
Referring to FIG. 2B, the first polycrystalline silicon layer 31 doped with impurities is formed on the etch-stop layer 27 by CVD (chemical vapor deposition), filling up the contact hole 29 and in contact with the source junction 15. A mask pattern 33 is defined by leaving a corresponding portion on the contact hole 29 after an oxide layer has been deposited on the first polycrystalline layer 31. Furthermore, a sidewall spacer 35 is formed on lateral sides of the mask pattern 33 by etching back a nitride layer which has been deposited on both surfaces of the polycrystalline layer 31 and an exposed surface of the mask pattern 33.
Referring to FIG. 2C, the first polycrystalline silicon layer 31 is patterned into a pillar shape by etching using the mask pattern 33 and the sidewall spacers 35, exposing the etch-stop layer 27. The remaining portion of the first polycrystalline silicon layer 31 is exposed by removing the mask pattern 33. Using the sidewall spacers 35 as a mask, the exposed part of the polycrystalline silicon layer 31 is etched into a shape of a cylinder or a crown, and the etch-stop layer 27 prevents the planarized layer 25 from being removed. The sidewall spacers 35 remaining on the first polycrystalline silicon layer 31 is then removed and at the same time the exposed portion of the etch-stop layer 27 is removed, and the remaining portion of the first polycrystalline silicon layer 31 becomes the storage electrode 31.
Referring to FIG. 2D, a dielectric film 37 is formed on the surface of the storage electrode 31 (the first polycrystalline silicon layer 31). The dielectric film 37 includes one of oxide, oxide/nitride, Ta.sub.2 O.sub.5, PZT (Pb(Zr Ti)O.sub.3) and BST ((Ba Sr)TiO.sub.3). A second polycrystalline silicon layer 39 doped with impurities is formed on the dielectric film 37 to form the plate electrode 39.
The conventional semiconductor device fabricated by the above method has a Diagonal Capacitor On Bit Line structure, increasing the capacitance due to the increased area of the capacitor by forming the bit line 23 before the formation of the capacitor and also simplifying the process by decreasing an aspect ratio of the contact hole 29 which causes difficulty in contacting the bit line 23.
However, as the DRAM cell having the Diagonal Capacitor On Bit Line structure and the logic device are formed on a single chip using the conventional method, the process gets complicated.
Moreover, since the large step difference between the DRAM cell area and the logic device area causes poor resolution in the process of forming a conductive line, a fine photoresist pattern is hard to define.